1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device using a double word line system and a negative voltage word line system.
2. Description of the Related Art
A demand for high integration of a memory cell is increasing with mass storage on a semiconductor memory device. To respond to the demand, a double word line system has been employed in which a sub-word line driving circuit is provided within a memory cell to divide a main word line composed of metal wiring into a plurality of sub-word lines consisting of polysilicon wiring so that the density of the word line is increased.
FIG. 9 is a block diagram showing a concept of the double word line system. Operations and approximate configurations of the word line system and its driving device in a semiconductor memory device using a double word line system are described hereafter by referring to FIG. 9. Bit lines and their related parts are not shown in the drawing.
A memory cell array 100 of the semiconductor memory device shown in FIG. 9 is provided with main row decoder circuits 101.sub.1, 101.sub.2 and so on, and sub row decoder circuits 102.sub.1, 102.sub.2 and so on. Any one of the main row decoder circuits 101.sub.1, 101.sub.2 and so on is selected depending on an internal address signal and a row decoder control signal. For example, if the main row decoder circuit 101.sub.1 is selected, the main word line MWL0 connected to the main row decoder circuit 101.sub.1 is activated. Any one of the sub row decoder circuits 102.sub.1, 102.sub.2 and so on is selected depending on the internal address signal and the row decoder control signal. For example, if the sub row decoder circuit 102.sub.1 is selected, it activates any one of the plural sub-word selection lines in accordance with the address signal. Each of sub-word line driving blocks 103.sub.11, 103.sub.12 and so on has, for example, 4 sub-word line driving circuits and a sub-word line driving circuit selected by a sub-word selection line activates the sub-word line, for example, SWL0 connected to the driving circuit.
The double word line system is used for the following reasons. When the word line is composed of polysilicon wiring, though its wiring pitch can be made small, because the polysilicon wiring is of high electrical resistance, wire delay time at the end of the wiring, if the wiring is long, is increased, thus causing the interference with the improvement of an operating speed of memory.
To solve this problem, the main word line is formed by using metal wiring, which is difficult to make its wiring pitch smaller but being of low electrical resistance, such as aluminum (Al) or the like, and a plurality of sub-word line driving blocks are provided within the memory array to connect memory cells using a short sub-word line extending from each of the sub-word line driving circuits. This enables an increase in word line density as well as in operating speed of memory.
Moreover, in the double word line system as shown in FIG. 9, by selecting the sub row decoder circuits in such a manner that one selected odd-numbered circuit is positioned in parallel with another selected odd-numbered circuit and one selected even-numbered circuit is positioned in parallel with another selected even-numbered circuit, the amount of data to be written and/or read can be increased accordingly.
FIG. 10 is a block diagram showing an example of configurations of a conventional semiconductor memory device. Slightly detailed configurations and operations of the conventional semiconductor memory device employing the double word line system are described below.
The conventional semiconductor memory device shown in FIG. 10 is so figured that it approximately comprises a main row decoder 111, a main word line 112 connected to the main row decoder 111, a sub row decoder circuit 113, a sub-word selection line 114 connected to the sub row decoder circuit 113, more than one, for example, four sub-word line driving circuits 115 constituting one sub-word line driving block connected to the sub-word selection lines 114, a sub-word line connected to each sub-word line driving circuit 115, two or more memory cells 117 horizontally connected to each sub-word line 116 and a bit line 118 vertically connected to each memory cell 117.
The main word line 112 is activated when the main row decoder circuit 111 is selected. Any one of the sub-word selection lines 114 is activated by the selection of the sub row decoder circuit 113 and, as a result, any one of the corresponding sub-word line driving circuits 115 is selected, which activates any one of the sub-word lines 116 connected to the selected sub-word line driving circuit 115. On the other hand, a bit line 118 is activated by a column driving circuit selected (not shown).
A cell transistor QM of the cell memory connected to the activated sub-word line 116 and the activated bit line 118 is turned ON when the sub-word line 116 becomes high (i.e., at a boosted power source potential Vpp) and either of a high-level voltage (power source potential Vcc) or a low-level voltage (ground potential GND) of the bit line is written on a cell capacitor CM, one end of which is connected to a terminal with 1/2 Vcc. The charge written on the cell capacitor CM, while the sub-word line 116 is low (i.e., at a ground potential), is held in the OFF state by the cell transistor QM.
In the semiconductor memory cell shown in FIG. 10, a threshold voltage Vtn of the cell transistor QM constituting the memory cell 117 is higher than that of peripheral transistors in order to reduce a subthreshold leakage current. Because of this, it is necessary to apply a voltage being higher than "sum of the threshold voltage Vtn of the cell transistor QM and the written voltage Vcc" to the sub-word line 116 connected to a gate of the transistor QM at the time of writing on the memory cell 117, and accordingly the boosted power source potential Vpp being higher than the power source potential Vcc is used as a high-level voltage of the sub-word line 116.
On the other hand, in order to respond to a demand for lowering the voltage to be used, which is increasing with mass storage on a semiconductor, a control of the boosted power source potential Vpp to a lower level is required. To do this, it is necessary to more lower the threshold voltage of the cell transistor QM. To prevent the degradation of hold characteristics of the memory cell attributable to a leakage current generated when the cell transistor QM is OFF which is specifically caused by the lowered threshold voltage Vtn, a negative potential Vnb has come to be instead used as a low-level voltage of the sub-word line 116. In this case, the negative voltage Vnb is conventionally fed by a power source having a voltage different from a substrate voltage. This is because the amount of currents consumed in the case of using the Vnb power source is large and there is a possibility of a great deal of noises caused by clutter at the Vnb potential and, accordingly, the Vnb power source has to be completely and electrically isolated from the Vbb power source to avoid adverse effects on the threshold voltage of the transistor.
FIG. 11 is a block diagram showing configurations of a word line driving system of a conventional semiconductor memory device. FIG. 12 shows levels of signals inputted when a word line is activated in the conventional sub-word line driving circuit.
The conventional word line driving system, as depicted in FIG. 11, is approximately composed of a main row decoder 121, a sub row decoder circuit 122, a sub-word line driving circuit 123 and a negative potential generating circuit 124.
As shown in FIG. 12, the main row decoder circuit 121, when a main word line is selected, is adapted to cause the main word line MWL to be at a boosted power source Vpp in response to an internal address signal and a row decoder circuit control signal and, when the main word line is not selected, to cause the main word line MWL to be at a negative potential Vnb.
Also, as shown in FIG. 12, the sub row decoder circuit 122, when a sub-word selection line is selected, is adapted to cause a sub-word selection line RA to be at a boosted power source potential Vpp and a sub-word selection line RAB to be at a negative potential Vnb in response to the internal address signal and row decoder circuit control signal and, while the sub-word selection line is not selected, to cause the sub-word selection line RA to be at a negative potential Vnb and the sub-word selection line RAB to be at a power source potential Vcc.
The sub-word line driving circuit 123, when both the main word line MWL and the sub-word selection lines RA/RAB are selected, is adapted to cause the sub-word line SWL to be at a boosted power source Vpp, and when either or both of the main word line MWL and the sub-word selection lines RA/RAB are not selected, to cause the sub-word line SWL to be at a negative potential Vnb. The negative potential generating circuit 124 feeds a negative voltage Vnb to a main row decoder circuit 121, a sub row decoder circuit 121 and a sub-word line driving circuit 123. The main row decoder circuit, sub row decoder circuit and sub-word line driving circuit form an X decoder circuit for driving a memory cell array in the direction of X (i.e., in the direction of a word line).
FIG. 13A shows the configuration of a conventional sub-word line driving circuit and FIG. 13B shows the operating timing chart in the conventional sub-word line driving circuit. As shown in FIG. 13A, the conventional sub-word line driving circuit has four N-channel transistors QN31, QN32, QN33 and QN34.
While the main word line MWL and the sub-word selection line RA/RAB are selected, the sub-word line SWL is in the state of writing data on a memory cell. This state is represented by FIG. 13B.
The potential of the main word line MWL, when the main row decoder circuit is selected by an input of an address, changes from its negative potential Vnb to its boosted power source potential Vpp. Since a gate of a transistor QN33 is provided with the boosted power source voltage Vpp, to a gate of a transistor QN31 is fed a voltage obtained by a formula "gate potential of transistor QN33--threshold potential of transistor QN33." At this point, if a potential of a selected sub-word selection line RA changes from Vnb to Vpp, the potential of the gate of the transistor QN31 rises, due to capacitive coupling, approximately to a potential obtained by a formula "gate potential of transistor QN33--threshold voltage of transistor QN33+Vpp-Vnb", and the voltage Vpp of the sub-word selection line RA is transmitted to the sub-word line SWL without any drop of its level.
After the completion of access, because the potential of the sub-word selection line RA changes from Vpp to Vnb and that of the sub-word selection line RAB changes from Vnb to Vcc, the potential of the sub-word line SWL changes from Vpp to Vnb. Then, the potential of the main word line MWL changes from Vpp to Vnb and the sub-word line driving circuit is restored to an unselected state.
While the main word line MWL and/or the sub-word selection lines RA/RAB are not selected, the memory cell is in a state of holding data. While the sub-word line is not selected, since the sub-word selection line RA is at a negative potential Vnb and the sub-word selection line RAB is at a power source potential Vcc, the transistor QN is turned ON and the sub-word line SWL is at a negative potential Vnb. This state remains unchanged even if the main word line MWL is selected or not selected. Moreover, when the main word line MWL is not selected (i.e., at a negative potential Vnb) and when the sub-word selection line RA is selected (i.e., at a boosted power source potential Vpp), in order to prevent the sub-word line SWL from being in a floating state, the sub-word line SWL is adapted to be maintained at the Vnb level by connecting the sub-word line SWL through the transistor QN34 to the main word line MWL.
FIG. 14 shows an example of configurations of a conventional main row decoder. The conventional main row decoder circuit, as shown in FIG. 14, is provided with a gate AND 41, P-channel transistors QP41, QP42, QP43 and QP44, N-channel transistors QN41, QN42, QN43 and QN44, and an inverter INV41.
When the main word line is selected, since all address inputs IN0, IN1, . . . , INm-1 go high and an output of the AND gate AND41 goes high, a transistor QN41 is turned ON and a potential of a connection point of the transistor QP41 and QN41 is at a ground potential GND, thus causing a transistor QP44 to be turned ON and a boosted power source voltage Vpp to be outputted to the main word line MWL.
On the other hand, while the main word line is not selected, since any one of the address inputs IN0, IN1, . . . , INm-1 does not become high, the output of the AND gate AND 41 goes low and a power source potential Vcc of the inverter 41 is fed to a gate of the transistor QN42 through the inverter INV41 and, as a result, the transistor QN42 is turned ON, causing a potential of a connection point of the transistor QP42 and QN42 is at a ground potential GND. This causes a transistor 43 to be turned ON and a potential of a connection point of the transistor QP43 and QN43 is at a boosted power source potential Vpp and, as a result, a transistor QN44 is turned ON and a negative voltage Vnb is outputted to the main word line MWL.
FIG. 15 shows an example of configurations of a conventional sub row decoder circuit. The conventional sub row decoder circuit, as shown in FIG. 15, is provided with an AND gate AND 51, P-channel transistors QP51, QP52, QP53 and QP54, N-channel transistors QN51, QN52, QN53 and QN54, and an inverter INV 51.
When the sub-word selection line is selected, since all address inputs IN0, IN1, . . . , INn-1 go high and an output of the AND gate AND51 goes high, a ground voltage GND is fed to a gate of the transistor QP52 through the inverter INV51 and the transistor QP52 is turned ON, and a potential of a connection point of the transistors QP52 and QN52 is at a power source potential Vcc, thus causing the transistor 53 to be turned ON and a connection point of the transistors QP53 and QN53 is at a negative potential Vnb and, as a result, the transistor QP54 is turned ON and a boosted power source voltage Vpp is outputted to the sub-word selection line RA.
Furthermore, when the point of connections of the transistors QP52 and QN52 is at the power source potential Vcc, the transistor QN51 is turned ON, causing the negative voltage Vnb to be outputted to the sub-word selection line RAB.
On the other hand, while the sub-word selection line is not selected, since any one of the address inputs IN0, IN1, . . . , INm-1 is not high, an output of the AND gate AND 51 goes low and a power source potential Vcc is outputted to the sub-word selection line RAB, causing the transistor QN54 to be turned ON and the negative voltage Vnb to be outputted to the sub-word selection line RA. At this point, the transistor QP54 is held in the OFF state.
As described above, the conventional semiconductor memory device presents a problem in that, due to its use of the negative voltage word line system, the maximum applied voltage between the gate and source and between the gate and drain of the transistor constituting the word line driving circuit is high. Moreover, there is a problem in that the consumption of currents of the negative power source in the memory cell array and of its peripheral circuits is large.
FIG. 16 shows the maximum applied voltage between the gate and source and between the gate and drain and the place where the voltage is applied as well as its input signal level in the conventional sub-word line driving circuit.
The maximum applied voltage between the gate and source and between the gate and drain in the sub-word line driving circuit shown in FIG. 13A occurs between the gate and the drain of the transistor QN32. At this point, the input signal level is the negative potential Vnb occurred when the sub-word selection line RAB is selected and the boosted power source potential Vpp occurred when the main word line MWL is selected, and the maximum applied voltage between the gate and source and between the gate and drain is Vpp+.vertline.Vnb.vertline.. For example, if the power source Vcc=1.8 V, the boosted power source voltage Vpp=2.5 V and the negative voltage Vnb=-0.5 V, the maximum applied voltage between the gate and source and between the gate and drain Vpp+.vertline.Vnb.vertline. is 3V, accordingly.
Thus, if the maximum applied voltage between the gate and source and between the gate and drain increases, in order to increase a withstand property against the voltage between the gate and source and between the gate and drain, the increase in the thickness of the oxide film at the gate is required. In this case, since the sub-word line driving circuit is mounted within the memory array, it is advantageous from a production viewpoint that the sub-word line driving circuit portion and the memory cell portion have the oxide film with the same thickness therein. However, if the oxide film is required to have such a large thickness as can withstand the increased maximum applied voltage between the gate and source and between the gate and drain, the thickness of the oxide film turns out to be too large with respect to the cell transistor, thus causing the threshold voltage of the cell transistor to drop and a leakage current while data is held to increase and unfavorably leading to the degradation of hold characteristics. Accordingly, it is necessary that the oxide film differs in thickness between the sub-word line driving circuit portion and the memory cell, which naturally makes the production process complex, inevitably causing the increase in the production cost.
Furthermore, as shown in FIG. 13B, in the conventional sub-word line driving circuit, since the negative potential Vnb is used as the low-level voltage of the main word line MWL and sub-word selection lines RA/RAB, the currents flow into the negative power source through the sub-word line driving circuit, causing the increase in the current consumption of the negative power source.